dx_firewire_ohci.h File Reference

This graph shows which files directly or indirectly include this file:

Namespaces
namespace	dx
	dynax driver framework interface namespace
namespace	dx::firewire
	IEEE 1394: what user mode and the kernel share.
namespace	dx::firewire::ohci
	the 1394 Open Host Controller Interface, release 1.1

Enumerations
enum	dx::firewire::ohci::context : unsigned int { dx::firewire::ohci::control_set = 0x000 , dx::firewire::ohci::control_clear = 0x004 , dx::firewire::ohci::command_ptr = 0x00c , dx::firewire::ohci::match = 0x010 }
	a context's registers by their offset into its set More...
enum	dx::firewire::ohci::event : unsigned int {   dx::firewire::ohci::req_tx_complete = 1u<< 0 , dx::firewire::ohci::resp_tx_complete = 1u<< 1 , dx::firewire::ohci::arrq = 1u<< 2 , dx::firewire::ohci::arrs = 1u<< 3 ,   dx::firewire::ohci::rq_pkt = 1u<< 4 , dx::firewire::ohci::rs_pkt = 1u<< 5 , dx::firewire::ohci::isoch_tx = 1u<< 6 , dx::firewire::ohci::isoch_rx = 1u<< 7 ,   dx::firewire::ohci::posted_write_err = 1u<< 8 , dx::firewire::ohci::lock_resp_err = 1u<< 9 , dx::firewire::ohci::self_id_complete2 = 1u<< 15 , dx::firewire::ohci::self_id_complete = 1u<< 16 ,   dx::firewire::ohci::bus_reset = 1u<< 17 , dx::firewire::ohci::reg_access_fail = 1u<< 18 , dx::firewire::ohci::phy = 1u<< 19 , dx::firewire::ohci::cycle_synch = 1u<< 20 ,   dx::firewire::ohci::cycle64_seconds = 1u<< 21 , dx::firewire::ohci::cycle_lost = 1u<< 22 , dx::firewire::ohci::cycle_inconsistent = 1u<< 23 , dx::firewire::ohci::unrecoverable_error = 1u<< 24 ,   dx::firewire::ohci::cycle_too_long = 1u<< 25 , dx::firewire::ohci::phy_reg_rcvd = 1u<< 26 , dx::firewire::ohci::master_int_enable = 1u<< 31 }
	IntEvent and IntMask (OHCI 1.1 6.1). More...
enum	dx::firewire::ohci::hc_control : unsigned int {   dx::firewire::ohci::soft_reset = 1u<< 16 , dx::firewire::ohci::link_enable = 1u<< 17 , dx::firewire::ohci::posted_write_enable = 1u<< 18 , dx::firewire::ohci::lps = 1u<< 19 ,   dx::firewire::ohci::a_phy_enhance_enable = 1u<< 22 , dx::firewire::ohci::program_phy_enable = 1u<< 23 , dx::firewire::ohci::no_byte_swap_data = 1u<< 30 , dx::firewire::ohci::bib_image_valid = 1u<< 31 }
	HCControl (OHCI 1.1 5.7): soft_reset reads one until the reset completed, lps powers the link - most registers answer only with it. More...
enum	dx::firewire::ohci::link_control : unsigned int { dx::firewire::ohci::rcv_self_id = 1u<< 9 , dx::firewire::ohci::rcv_phy_pkt = 1u<< 10 , dx::firewire::ohci::cycle_timer_enable = 1u<< 20 , dx::firewire::ohci::cycle_master = 1u<< 21 }
	LinkControl (OHCI 1.1 5.10). More...
enum	dx::firewire::ohci::node : unsigned int { dx::firewire::ohci::node_number = 0x3f , dx::firewire::ohci::node_root = 1u<< 30 , dx::firewire::ohci::node_valid = 1u<< 31 }
	NodeID (OHCI 1.1 5.11). More...
enum	dx::firewire::ohci::offset : unsigned int {   dx::firewire::ohci::version = 0x000 , dx::firewire::ohci::guid_rom = 0x004 , dx::firewire::ohci::at_retries = 0x008 , dx::firewire::ohci::csr_read_data = 0x00c ,   dx::firewire::ohci::csr_compare_data = 0x010 , dx::firewire::ohci::csr_control = 0x014 , dx::firewire::ohci::config_rom_header = 0x018 , dx::firewire::ohci::bus_id = 0x01c ,   dx::firewire::ohci::bus_options = 0x020 , dx::firewire::ohci::guid_hi = 0x024 , dx::firewire::ohci::guid_lo = 0x028 , dx::firewire::ohci::config_rom_map = 0x034 ,   dx::firewire::ohci::posted_write_address_lo = 0x038 , dx::firewire::ohci::posted_write_address_hi = 0x03c , dx::firewire::ohci::vendor_id = 0x040 , dx::firewire::ohci::hc_control_set = 0x050 ,   dx::firewire::ohci::hc_control_clear = 0x054 , dx::firewire::ohci::self_id_buffer = 0x064 , dx::firewire::ohci::self_id_count = 0x068 , dx::firewire::ohci::ir_multi_channel_mask_hi_set = 0x070 ,   dx::firewire::ohci::ir_multi_channel_mask_hi_clear = 0x074 , dx::firewire::ohci::ir_multi_channel_mask_lo_set = 0x078 , dx::firewire::ohci::ir_multi_channel_mask_lo_clear = 0x07c , dx::firewire::ohci::int_event_set = 0x080 ,   dx::firewire::ohci::int_event_clear = 0x084 , dx::firewire::ohci::int_mask_set = 0x088 , dx::firewire::ohci::int_mask_clear = 0x08c , dx::firewire::ohci::iso_xmit_int_event_set = 0x090 ,   dx::firewire::ohci::iso_xmit_int_event_clear = 0x094 , dx::firewire::ohci::iso_xmit_int_mask_set = 0x098 , dx::firewire::ohci::iso_xmit_int_mask_clear = 0x09c , dx::firewire::ohci::iso_recv_int_event_set = 0x0a0 ,   dx::firewire::ohci::iso_recv_int_event_clear = 0x0a4 , dx::firewire::ohci::iso_recv_int_mask_set = 0x0a8 , dx::firewire::ohci::iso_recv_int_mask_clear = 0x0ac , dx::firewire::ohci::initial_bandwidth_available = 0x0b0 ,   dx::firewire::ohci::initial_channels_available_hi = 0x0b4 , dx::firewire::ohci::initial_channels_available_lo = 0x0b8 , dx::firewire::ohci::fairness_control = 0x0dc , dx::firewire::ohci::link_control_set = 0x0e0 ,   dx::firewire::ohci::link_control_clear = 0x0e4 , dx::firewire::ohci::node_id = 0x0e8 , dx::firewire::ohci::phy_control = 0x0ec , dx::firewire::ohci::cycle_timer = 0x0f0 ,   dx::firewire::ohci::async_request_filter_hi_set = 0x100 , dx::firewire::ohci::async_request_filter_hi_clear = 0x104 , dx::firewire::ohci::async_request_filter_lo_set = 0x108 , dx::firewire::ohci::async_request_filter_lo_clear = 0x10c ,   dx::firewire::ohci::physical_request_filter_hi_set = 0x110 , dx::firewire::ohci::physical_request_filter_hi_clear = 0x114 , dx::firewire::ohci::physical_request_filter_lo_set = 0x118 , dx::firewire::ohci::physical_request_filter_lo_clear = 0x11c ,   dx::firewire::ohci::physical_upper_bound = 0x120 , dx::firewire::ohci::at_request = 0x180 , dx::firewire::ohci::at_response = 0x1a0 , dx::firewire::ohci::ar_request = 0x1c0 ,   dx::firewire::ohci::ar_response = 0x1e0 }
	the registers by their offset into BAR 0 (OHCI 1.1 table 4-3); a Set/Clear pair writes ones to set or clear bits and reads the register More...
enum	dx::firewire::ohci::phy_access : unsigned int { dx::firewire::ohci::phy_write = 1u<< 14 , dx::firewire::ohci::phy_read = 1u<< 15 , dx::firewire::ohci::phy_read_done = 1u<< 31 }
	PhyControl (OHCI 1.1 5.12): a register's address at bits 11..8, written data at 7..0, read data at 23..16. More...
enum	dx::firewire::ohci::self_id : unsigned int { dx::firewire::ohci::self_id_error = 1u<< 31 }
	SelfIDCount (OHCI 1.1 11.2): the generation at bits 23..16, the quadlets at 10..2. More...

Functions
constexpr offset	dx::firewire::ohci::ir(unsigned int n)
constexpr offset	dx::firewire::ohci::it(unsigned int n)
	the register set of isochronous transmit and receive context n
constexpr unsigned int	dx::firewire::ohci::retries(unsigned int request, unsigned int response, unsigned int physical, unsigned int cycles)
	ATRetries (OHCI 1.1 5.4): the retries of a request, a response and a physical response, the cycles a busy retry waits at most.